Driving circuit for a shared sense amplifier with increased speed clock generation circuit for reading addressed memory cells

ABSTRACT

A cut-off clock φ 5  generated by a cut-off clock generation circuit PG is supplied to a decode circuit DEC. The decode circuit DEC decodes the cut-off clock φ 5  to produce two types of cut-off clocks φ 5L  and φ 5R . The two types of cut-off clocks φ 5L  and φ 5R  are supplied to a control clock generation circuit as shown in FIG. 3 or 11, which in turn produces control clocks φ 2L  and φ 2R . The control clocks φ 2L  and φ 2R  are supplied to a shared sense amplifier of FIG. 1, to control on-off operations of transfer transistors 7 L , 8 L , 7 R  and 8 R .

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a driving circuit for a shared senseamplifier, and more particularly, it relates to a circuit for driving asense amplifier shared by two pairs of bit lines at a high speed.

2. Description of the Prior Art

FIG. 1 shows an example of a shared sense amplifier to which the presentinvention can be applied. In FIG. 1, a clock φ₃ is supplied torespective sources of transistors 1 and 2. The drain of the transistor 1is connected to a sense node 9 while the gate thereof is connected to asense node 10. On the other hand, the drain of the transistor 2 isconnected to the sense node 10 while the gate thereof is connected tothe sense node 9. These transistors 1 and 2 form a flip-flop type senseamplifier.

One end of the sense node 9 is connected to a bit line 3_(R) through atransfer transistor 7_(R) while the other end thereof is connected to abit line 3_(L) through a transfer transistor 7_(L). One end of the sensenode 10 is connected to a bit line 4_(R) through a transfer transistor8_(R) while the other end thereof is connected to a bit line 4_(L)through a transfer transistor 8_(L). The transfer transistors 7_(R) and8_(R) are adapted to connect and cut off the bit lines 3_(R) and 4_(R)on the right side with and from the sense amplifier, and are on-offcontrolled by a control clock φ_(2R). Similarly, the transfertransistors 7_(L) and 8_(L) are adapted to connect and cut off the bitlines 3_(L) and 4_(L) on the left side with and from the senseamplifier, and are on-off controlled by a control clock φ_(2L). The bitlines 3_(R) and 4_(R) form a pair of folded bit lines while the bitlines 3_(L) and 4_(L) similarly form another pair of folded bit lines.In the shared sense amplifier circuit as shown in FIG. 1, the senseamplifier, which is formed by the transistors 1 and 2, is shared by thetwo pairs of folded bit lines.

The bit lines 3_(R) and 4_(R) on the right side of FIG. 1 arerespectively connected with sources of transistors 5_(R) and 6_(R).Precharge voltage V_(R) is applied to respective drains of thetransistors 5_(R) and 6_(R) while a precharge clock φ_(1R) is suppliedto respective gates thereof. These transistors 5_(R) and 6_(R) areadapted to charge the bit lines 3_(R) and 4_(R) at the precharge voltageV_(R) in response to the precharge clock φ_(1R) respectively. The bitlines 3_(R) and 4_(R) are further connected with memory cells MC_(1R)and MC_(NR) respectively. The storage content of the memory cell MC_(1R)is read on the bit line 3_(R) when a word line WL_(1R) is selected whilethe storage content of the memory cell MC_(NR) is read on the bit line4_(R) when a word line WL_(NR) is selected. The bit lines 3_(R) and4_(R) are further connected with dummy memory cells DC_(1R) and DC_(2R).With respect to the dummy memory cell DC_(1R), intermediate potentialbetween read out potential of information "0" and that of information"1" is read on the bit line 3_(R) when a dummy word line DWL_(1R) isselected, while the said intermediate potential is read on the bit line4_(R) when a dummy word line DWL_(2R) is selected with respect to thedummy memory cell DC_(2R).

Elements similar to those connected with the bit lines 3_(R) and 4_(R)are connected with the bit lines 3_(L) and 4_(L) on the left side. Theelements corresponding to the aforementioned ones are indicated by thesame reference numerals, except for that the subscripts "R" are replacedby "L", and detailed description thereof is herein omitted.

The bit lines 3_(L) and 4_(L) on the left side are connected withread/write lines I/O₁ and I/O₂ respectively through transfer transistors11 and 12. A clock φ₄ is supplied to respective gates of the transfertransistors 11 and 12.

Although merely four word lines WL_(1R), WL_(NR), WL_(1L) and WL_(NL)are shown in FIG. 1, a number N (arbitrarily selected even number) ofword lines are present on each side in practice while the number N ofmemory cells MC_(1R) (MC_(1L)) to MC_(NR) are connected with the bitlines 3_(R) (3_(L)) and 4_(R) (4_(L)) by N/2 respectively.

Although the circuit as shown in FIG. 1 employs only one senseamplifier, a practical memory is generally formed by a plurality ofsense amplifiers which are vertically aligned to form arrays of memorycells.

Description is now made on a circuit having one sense amplifier and twoword lines, for easy understanding of the present invention.

FIG. 2 is a timing chart of an NMOS employed for illustrating theoperation of the circuit as shown in FIG. 1.

In a standby state to a time T₁, the precharge clock φ_(1L) is at a highlevel, whereby the transistors 5_(L) and 6_(L) are in ON states and thebit lines 3_(L) and 4_(L) are charged at the precharge voltage V_(L).The precharge clock φ_(1R) is also at a high level, whereby the bitlines 3_(R) and 4_(R) are charged at the precharge voltage V_(R) throughthe transistors 5_(R) and 6_(R). During this period, the clock φ₃ forinactivating the sense amplifier is at a high level, whereby the senseamplifier is retained in the standby state. Assuming here that either ofthe memory cells MC_(1R) and MC_(NR) on the right side of the senseamplifier is addressed by address data (not shown), the potential ofeither word line WL_(1R) or WL_(NR) and that of either dummy word lineDWL_(1R) or DWL_(2R) are increased, while the non-selected word lineWL_(1L) or WL_(NL) and dummy word line DWL_(1L) or DWL_(2L) remain atlow levels.

The potential levels at the selected word line and dummy word line arenot immediately increased upon the addressing performed by the addressdata. This is because the address data are supplied to a decoder (notshown), which increases the potential levels at the selected word lineand dummy word line, whereby the increase in the potential levels of theword line and dummy word line is delayed from the addressing by the timerequired for processing in the decoder.

Description is now made on the case where, for example, the word lineWL_(1R) and dummy word line DWL_(2R) are selected.

Upon input of the address data, the control clock φ_(2L) is turned to alow level at a time T₂ before increase of the potential levels at theword line WL_(1R) and dummy word line DWL_(2R), whereby the transfertransistors 7_(L) and 8_(L) are both made nonconductive. Thus, the sensenodes 9 and 10 are electrically cut off from the bit lines 3_(L) and4_(L), and the potential levels at the word line WL_(1R) and dummy wordline DWL_(2R) are increased at a time T₃. Then, information stored inthe memory cell MC_(1R) is read on the bit line 3_(R) and the chargestored in the dummy memory cell DC_(2R) is read on the bit line 4_(R)respectively. The read information is transferred to the sense nodes 9and 10 through the transfer transistors 7_(R) and 8_(R) during theperiod when the control clock φ_(2R) is at a high level to a time T₄.The level of the control clock φ_(2R) slightly drops at the time T₄while impedance levels of the transfer transistors 7_(R) and 8_(R) areincreased. When the clock φ₃ is turned to a low level at a time T₅, thesense amplifier formed by the transistors 1 and 2 is activated and theinformation transferred to the sense nodes 9 and 10 is amplified. Theamplified information is returned to the bit lines 3_(R) and 4_(R)respectively through the transfer transistors 7_(R) and 8_(R), to bere-written in the memory cell being selected. The control clock φ_(2L)is again turned to a high level at a time T₆, whereby the amplifiedinformation is transferred to the bit lines 3_(L) and 4_(L) through thetransfer transistors 7_(L) and 8_(L).

The clock φ₄ is turned to a high level at a time T₇, and the amplifiedinformation is transferred to the read/write lines I/O₁ and I/O₂ throughthe transfer transistors 11 and 12. The word line WL_(1R), dummy wordline DWL_(2R) and clock φ₄ return to low levels at a time T₈ and theclocks φ_(1R), φ_(1L), φ₃ and φ_(2R) are turned to high levels at a timeT₉, whereby the folded bit lines on both sides are charged at V_(R) andV_(L) respectively, and the sense amplifier returns to a standby state.

The sequential read/write operation is performed in the aforementionedmanner. The impedance levels of the transfer transistors 7_(R) and 8_(R)are so increased in amplification of the sense amplifier as to reducecapacitive loads at the sense nodes 9 and 10 thereby to increaseamplification sensitivity.

When the memory cells MC_(1L) and MC_(NL) on the left side are selected,the waveforms of the control clocks φ_(2L) and φ_(2R) change places witheach other.

As hereinabove described, the sense amplifier as shown in FIG. 1 isdriven to be shared by two pairs of folded bit lines.

As obvious from the foregoing description, the waveforms of the controlclocks φ_(2R) and φ_(2L) have important functions for driving the sharedsense amplifier. Particularly the control clock on the non-selected side(φ_(2L) in the above case) must be immediately turned to a low levelbefore the potential levels at the selected word lines rise upon theaddressing of the memory cells by the address data, i.e., beforeread-out of the memory cells, to cut off the non-selected bit lines fromthe sense amplifier. Slow fall of the control clock on the non-selectedside delays the read-out from the memory cells, whereby high-speedread-out is disabled. Thus, awaited is implementation of a drivingcircuit for a shared sense amplifier which can attain high-speed readoutoperation by quickly connecting and cutting off bit lines with and fromthe sense amplifier.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a driving circuit for asense amplifier shared by two pairs of bit lines which can connect andcut off the bit lines with and from the sense amplifier at a high speedthereby to drive the shared sense amplifier at a high speed.

Briefly stated, the present invention provides a circuit for driving ata high speed a shared sense amplifier including two pairs of bit linesrespectively connected with memory cells, a sense amplifier positionedbetween the two pairs of bit lines for amplifying information read fromthe memory cells, first switch means interposed between one of the pairsof bit lines and the sense amplifier and second switch means interposedbetween the other pair of bit lines and the sense amplifier thereby toshare the sense amplifier by the two pairs of bit lines, and the drivingcircuit comprises a cut-off clock generation circuit, a decoder and ancontrol clock generation circuit. The cut-off clock generation circuitis adapted to generate a cut-off clock which responds at a high speed toaddressing of the memory cells, and the decoder is adapted to decode thecut-off clock from the cut-off clock generation circuit while thecontrol clock generation circuit is adapted to generate a control clockfor controlling the on-off operation of the first switch means and acontrol clock for controlling the on-off operation of the second switchmeans on the basis of the output from the decoder. The aforementionedcut-off clock generation circuit includes a first potential levelsource, a second potential level source, a first transistor whoseconducting terminal is connected at one end to the first potential levelsource, a second transistor interposed between the other end of theconducting terminal of the first transistor and the second potentialsource, a first circuit means for making the first transistor conductiveand the second transistor non-conductive in response to addressing ofthe memory cell, a capacitor means for boosting interposed between theother end of the conducting terminal and the gate terminal of the firsttransistor and a second circuit means for producing a cut-off clock onthe basis of potential change at the other end of the conductingterminal of the first transistor.

Generated according to the present invention is the cut-off clock whichresponds at a high speed to the addressing to produce a control clockfrom the cut-off clock, thereby to control on-off operations of thefirst and second switch means by the control clock, and hence the bitlines on the non-selected side can be cut off from the sense amplifierimmediately upon the addressing of the memory cell. Therefore, even ifthe time interval from the addressing of the memory cell to actualread-out of the information in the memory cell is extremely short, thebit lines on the non-selected side can reliably be cut off from thesense amplifier within the short interval, thereby to attain high-speeddriving of the shared sense amplifier.

The above and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an example of a shared senseamplifier to which the present invention can be applied;

FIG. 2 is a timing chart for illustrating the operation of the circuitas shown in FIG. 1;

FIG. 3 is a circuit diagram showing a part of a control clock generationcircuit according to an embodiment of the present invention;

FIG. 4 is a timing chart for illustrating the operation of the circuitas shown in FIG. 3;

FIG. 5 is a block diagram showing a circuit for generating a cut-offclock to be supplied to the circuit as shown in FIG. 3;

FIG. 6 is a diagram showing an example of definite circuit structure ofthe cut-off clock generation circuit as shown in FIG. 5;

FIG. 7 is a timing chart for illustrating the operation of the circuitas shown in FIG. 6;

FIG. 8 is a diagram showing an example of definite circuit structure ofa decode circuit as shown in FIG. 5;

FIG. 9 is a timing chart for illustrating the operation of the circuitas shown in FIG. 8;

FIG. 10 is a waveform diagram for illustrating problems caused when thecircuit as shown in FIG. 3 is employed;

FIG. 11 is a circuit diagram showing another example of the controlclock generation circuit; and

FIG. 12 is a timing chart for illustrating the operation of the circuitas shown in FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 shows a part of a control clock generation circuit according toan embodiment of the present invention. In FIG. 3, the said circuitincludes transistors Q₁ to Q₃ and a capacitor C₁. The transistors Q₁ andQ₃ are connected in parallel with each other, and respective drainsthereof receive supply voltage V_(CC). The gate of the transistor Q₁receives a precharge clock φ_(1L) while the gate of the transistor Q₃receives an inverted delay clock φ₃ ', which is an inverted delay signalof the clock φ₃. Respective sources of the transistors Q₁ and Q₃ areconnected in common to an output terminal 13 and grounded through thedrain and source of the transistor Q₂. The output terminal 13 outputs acontrol clock φ_(2L). The gate of the transistor Q₂ receives a cut-offclock φ_(5L) as hereinafter described. One end of the capacitor C₁receives the clock φ₃ while the other end thereof is connected with theoutput terminal 13.

FIG. 3 shows the circuit for generating the control clock φ_(2L), and acircuit for generating a clock φ_(2R) is in similar structure to thatshown in FIG. 3, except for that a precharge clock φ_(1R) is supplied inplace of the precharge clock φ_(1L) and a cut-off clock φ_(5R) issupplied in place of the cut-off clock φ_(5L).

FIG. 4 is a timing chart for illustrating the operation of the circuitas shown in FIG. 3. Referring now to FIG. 4, description is made on theoperation of the circuit as shown in FIG. 3, in the case where addressedis the memory cell on the right side of the sense amplifier as shown inFIG. 1.

In the standby state to the time T₁, the clocks φ_(1L) and φ₃ are athigh levels, and the output terminal 13 and, thus, the control clockφ_(2L) are precharged at higher levels than the supply voltage V_(CC) bycapacitive coupling of the capacitor C₁ as hereinafter described. Then,at the time T₁, the precharge clock φ_(1L) is turned to a low level andthe transistor Q₁ is turned off, while the control clock φ_(2L) isretained at a high level until the cut-off clock φ_(5L) is turned to ahigh level at a time T₂. At the time T₂, the cut-off clock φ_(5L) isturned to a high level whereby the transistor Q₂ is turned on to groundthe output terminal 13. Therefore, the control clock φ_(2L) falls to alow level. At a time T₅, the clock φ₃ is turned to a low level. And at atime T₆, the inverted delay clock φ₃ ' is turned to a high level wherebythe transistor Q₃ is turned on. At this time, the cut-off clock φ_(5L)drops to a low level, whereby the transistor Q₂ is turned off and thecontrol clock φ_(2L) rises to the supply voltage V_(CC). At a time T₉,the clock φ₃ is turned to a high level, whereby the control clock φ_(2L)is boosted to the precharge level by capacitive coupling of thecapacitor C₁.

On the other hand, in the circuit for generating the control clockφ_(2R), the control clock φ_(2R) is retained at a high level to the timeT₂ similarly to the aforementioned control clock φ_(2L). However, thecut-off clock φ_(5R) still remains at a low level at the time T₂, andhence the control clock φ_(2R) is retained at a high level. At the timeT₅, the clock φ₃ falls to a low level, whereby the level of the controlclock φ_(2R) is lowered to the supply voltage V_(CC) by capacitivecoupling of the capacitor C₁. Then, at the time T₉, the clock φ₃ isturned to a high level, whereby the control clock φ_(2R) is boosted tothe original precharge level by capacitive coupling of the capacitor C₁.

In the case where the memory cell on the left side of the senseamplifier as shown in FIG. 1 is selected, simply the operation of thecircuit for generating the control clock φ_(2L) as hereinabove describedis replaced by that of the circuit for generating the control clockφ_(2R).

In order to make the control clock φ_(2L) or φ_(2R) fall at a highspeed, required is a circuit for making the cut-off clock φ_(5L) orφ_(5R) fall at a high speed. Description is now made on an example ofstructure of such a circuit.

FIG. 5 is a block diagram showing a circuit for generating a cut-offclock to be supplied to the circuit as shown in FIG. 3.

The circuit as shown in FIG. 5 is formed by two portions of a cut-offclock generation circuit PG for generating a cut-off clock φ₅ athigh-speed responsive to the addressing of the memory cells by theaddress data and a decode circuit for decoding the clamp clock φ₅thereby to generate two types of cut-off clock φ_(5L) and φ_(5R).

FIG. 6 is a circuit diagram showing an example of definite structure ofthe cut-off clock generation circuit PG as shown in FIG. 5. In FIG. 6,the circuit includes transistors M₁ to M₁₁ and a capacitor C₂. The drainof the transistor M₁ receives the supply voltage V_(CC) and the gatereceives the precharge clock φ₁ while the source is connected to a nodeN₁. The drain of the transistor M₂ is connected to the node N₁ and thegate receives a first address clock φ_(A) while the source is grounded.The drain of the transistor M₃ is connected to the node N₁ while thegate receives a second address clock φ_(A) and the source is grounded.The drain of the transistor M₄ receives an inverted precharge clock φ₁which is an inverted signal of the precharge clock φ₁ and the gate isconnected with the node N₁ while the source is connected with a node N₂.The drain of the transistor M₅ is connected with the node N₂ and thegate receives the inverted delay clock φ₃ ' while the source isgrounded. The drain of the transistor M₆ receives the supply voltageV_(CC) and the gate is connected to the node N₂ while the source isconnected to a node N₃. The drain of the transistor M₇ is connected withthe node N₃ while the gate receives the inverted delay clock φ₃ ' andthe source is grounded. The drain of the transistor M₈ is connected withthe node N₃ and the gate is connected with the node N₁ while the sourcethereof is grounded. The drain of the transistor M₉ receives the supplyvoltage V_(CC) while the gate is connected with the node N₃ and thesource is connected with an output terminal 14, which outputs thecut-off clock φ₅. The drain of the transistor M₁₀ is connected with theoutput terminal 14 and the gate is connected with the node N₁, while thesource is grounded. The drain of the transistor M₁₁ is connected withthe output terminal 14, while the gate receives the inverted delay clockφ₃ ', and the source is grounded. One end of the capacitor C₂ isconnected with the node N₂ and the other end thereof is connected withthe node N₃.

Either of the precharge clocks φ_(1L) and φ_(1R) as shown in FIG. 1 mayserve as the precharge clock φ₁. Or, alternatively, an address strobesignal may be employed in place of the precharge clock φ₁. Further, thefirst and second address clocks φ_(A) and φ_(A) are formed by partialbits extracted from the address data for addressing the memory cell, andthe first address clock φ_(A) indicates addressing of the memory cell onthe right side of the sense amplifier in FIG. 1 while the second addressclock φ_(A) indicates addressing of the memory cell on the left side ofthe sense amplifier in FIG. 1. In other words, the first address clockφ_(A) is turned to a high level when the memory cell on the right sideis addressed while the second address clock φ_(A) is turned to a highlevel when the memory cell on the left side is addressed.

FIG. 7 is a timing chart for illustrating the operation of the circuitas shown in FIG. 6. The operation of the circuit in FIG. 6 is nowdescribed with reference to FIG. 7. In the standby state to the time T₁,the precharge clock φ₁ is at a high level and the node N₁ is prechargedat a high level through the transistor M₁. Therefore, the transistorsM₄, M₈ and M₁₀ are in ON states and the nodes N₂ and N₃ and cut-offclock φ₅ are at low levels. At the time T₁, the precharge clock φ₁ isturned to a low level and the inverted precharge clock φ₁ is turned to ahigh level whereby the transistor M₁ is turned off while the node N₁remains at a high level, and hence the transistor M₄ is retained in anON state. Therefore, the high-level inverted precharge clock φ₁ issupplied to the node N₂, which is turned to a high level whereby thetransistor M₆ is turned on. However, since the node N₁ remains at a highlevel, the transistor M₈ is retained in an ON state and the node N₃ isretained at a low level. At the time T₂, either the first or secondaddress clock φ_(A) or φ_(A) is turned to a high level whereby eitherthe transistor M₂ or M₃ is turned on to turn the node N₁ to a low level.Therefore, the transistor M₄ is turned off and the node N₂ enters a highfloating state. On the other hand, the transistors M₈ and M₁₀ are turnedoff whereby the level of the node N₃ begins to be increased. Then thenode N₂ is boosted to a higher level by capacitive coupling of thecapacitor C₂, whereby the transistor M₆ is strongly turned on toincrease the voltage at the node N₃ to the level of the supply voltageV_(CC) at a high speed. Thus, the transistor M₉ is turned on to turn thecut-off clock φ₅ to a high level at a high speed. Then, at the time T₆,the inverted delay lock φ₃ ' is turned to a high level, whereby thetransistors M₅, M₇ and M₁₁ are turned on to turn the nodes N₂ and N₃ andcut-off clock φ₅ to low levels. Although the inverted delay clock φ₃ 'is employed in this embodiment to reset the circuit, such resetoperation may be performed by other types of reset clocks.

According to the circuit of FIG. 6 as hereinabove described, generatedis the clamp clock φ₅ which responds at a high speed to the first orsecond address clock φ_(A) or φ_(A).

FIG. 8 is a circuit diagram showing an example of definite structure ofthe decode circuit DEC as shown in FIG. 5, particularly the structure ofa circuit for producing the cut-off clock φ_(5L). The circuit as shownin FIG. 8 includes transistors M₁₂ to M₁₈. The drain of the transistorM₁₂ receives the supply voltage V_(CC) while the gate receives theprecharge clock φ₁ and the source is connected with a node N₄. The drainof the transistor M₁₃ is connected to the node N₄ while the gatereceives a second address clock φ_(A) and the source is grounded. Thedrain of the transistor M₁₄ receives the cut-off clock φ₅ from thecircuit as shown in FIG. 6 while the gate is connected with the node N₄and the source is connected with an output terminal 15, which outputsthe cut-off clock φ_(5L). The drain of the transistor M₁₅ is connectedwith the output terminal 15 and the gate is connected with a node N₅while the source is grounded. The drain of the transistor M₁₆ receivesthe supply voltage V_(CC) and the gate receives the precharge clock φ₁while the source is connected with the node N₅. The drain of thetransistor M₁₇ is connected with the node N₅ and the gate is connectedwith the output terminal 15 while the source is grounded. The drain ofthe transistor M₁₈ is connected with the output terminal 15 while thegate receives a cut-off clock φ_(5R) and the source is grounded.

A circuit for producing the cut-off clock φ_(5R) (similarly included inthe decode circuit) is in similar structure to the aforementionedcircuit as shown in FIG. 8, except for that the first address clockφ_(A) is supplied in place of the second address clock φ_(A) and thecut-off clock φ_(5L) is supplied in place of the cut-off clock φ_(5R).

FIG. 9 is a timing chart for illustrating the operation of the circuitas shown in FIG. 8. The operation of the circuit in FIG. 8 is nowdescribed with reference to FIG. 9, on such case that the memory cell onthe right side of the sense amplifier in FIG. 1 is addressed.

In the standby state to the time T₁, the precharge clock φ₁ is at a highlevel. Therefore, the transistors M₁₂ and M₁₆ are in ON states and thenodes N₄ and N₅ are precharged at high levels. Thus, the transistors M₁₄and M₁₅ are turned on and the output terminal 15 and, thus, the cut-offclock φ_(5L) at low levels. If the memory cell on the right side in FIG.1 is addressed at the time T₂, the first address clock φ_(A) is turnedto a high level while the second address clock φ_(A) remains at a lowlevel. Therefore, the node N₄ is retained at a high level at the timeT₂, thereby to retain the transistor M₁₄ in an ON state. Thus, the levelof the cut-off clock φ₅ is directly transmitted to the output terminal15, and the cut-off clock φ_(5L) presents the same waveform as that ofthe cut-off clock φ₅. At this time, the transistor M₁₇ is turned on toturn the node N₅ to a low level, whereby the transistor M₁₅ is in an OFFstate.

On the other hand, in the circuit for producing the cut-off clockφ_(5R), the first address clock φ_(A) rises to a high level at the timeT₂, whereby the transistor M₁₃ is turned on and the node N₄ is turned toa low level while the transistor M₁₄ is cut off. Thus, the level of thecut-off clock φ₅ is not transmitted to the output terminal 15, and thetransistor M₁₇ is not turned on. Therefore, the transistor M₁₅ remainsin an ON state and the cut-off clock φ_(5R) is retained at a low level.Further, during the period when the cut-off clock φ_(5L) is at a highlevel, the transistor M₁₈ is in an ON state whereby the cut-off clockφ_(5R) is securely retained at a low level state at least in thehigh-level period of the cut-off clock φ_(5L).

In the case where the memory cell on the left side of the circuit asshown in FIG. 1 is selected, the operation of the circuit for producingthe cut-off clock φ_(5L) is simply replaced by the operation of that forproducing the cut-off clock φ_(5R).

In the case where the circuit as shown in FIG. 3 is employed, it isnecessary to pull out the charge stored in the capacitor C₁ when thetransistor Q₂ is turned on to make the control clock φ_(2L) (φ_(2R))drop to a low level, and the dropping to the low level is delayed by thepull-out time. Further, as shown in FIG. 10, when the level of thecontrol clock φ_(2L) (φ_(2R)) is changed, the clock φ₃ may include anoise by the coupling of the capacitor C₁. Description is now made on anexample of circuit structure which overcomes the problems in the circuitof FIG. 3 and enables the cut-off operation at a higher speed with nonoise being included in the clock φ₃.

FIG. 11 shows an example of structure of a circuit which is improved toovercome the problems caused in the circuit as shown in FIG. 3. In thecircuit as shown in FIG. 11, a clock φ_(6L) (φ_(6R)) is supplied inplace of the clock φ₃ supplied to the capacitor C₁ in FIG. 3. The clockφ_(6L) (φ_(6R)) is produced by transistors Q₄ to Q₆. The drain of thetransistor Q₄ receives supply voltage V_(CC) and the gate receives aprecharge clock φ₁ while the source is connected with an output terminal16, which outputs the clock φ_(6L) (φ_(6R)). The drain of the transistorQ₅ is connected with the output terminal 16 and the gate receives theclock φ_(5L) (φ_(5R)) while the source is grounded. The drain of thetransistor Q₆ is connected with the output terminal 16 while the gatereceives a clock φ₃, which is an inverted signal of the aforementionedclock φ₃ and the source is grounded. The clock φ_(6L) (φ_(6R)) outputtedfrom the output terminal 16 is supplied to a capacitor C₁.

FIG. 12 is a timing chart for illustrating the operation of the circuitas shown in FIG. 11. Description is now made on the operation of thecircuit of FIG. 11 with reference to FIG. 12.

The operation of the circuit for producing the control clock φ_(2L) isnow described. In the standby state to the time T₁, the precharge clockφ₁ is at a high level and the clocks φ₃ and φ₅ are at low levels.Therefore, the transistors Q₁ and Q₄ are in ON states while thetransistors Q₂, Q₅ and Q₆ are in OFF states. Thus, the control clockφ_(2L) and clock φ_(6L) are retained at high levels. At the time T₁, theprecharge clock φ₁ is turned to a low level and the transistors Q₁ andQ₄ are turned off, whereas the clocks φ_(2L) and φ_(6L) are retained athigh levels since the transistors Q₂, Q₅ and Q₆ are retained in OFFstates. Then, at the time T₂, the cut-off clock φ_(5L) is turned to ahigh level and the transistors Q₂ and Q₅ are turned on, whereby thecontrol clock φ_(2L) and φ_(6L) drop to low levels. At this time, thecharge stored in the capacitor C₁ is pulled out from both sides of theoutput terminals 13 and 16, whereby the control clock φ_(2L) is made todrop to a low level at a higher speed than that in the circuit shown inFIG. 3. The operation thereafter is similar to that of the circuit asshown in FIG. 3.

Description is now made on the circuit for producing the control clockφ_(2R). Similarly to the aforementioned clocks φ_(2L) and φ_(6L), thecontrol clocks φ_(2R) and φ_(6R) are retained at high levels to the timeT₂. Since the cut-off clock φ_(5R) is still at a low level at the timeT₂, the control clock φ_(2R) and the clock φ_(6R) remain at high levels.At the time T₅, the clock φ₃ drops to a low level and the inverted clockφ₃ thereof is turned to a high level, whereby the transistor Q₆ isturned on to make the clock φ_(6R) drop to a low level. Therefore, thelevel of the control clock φ_(2R) is slightly lowered by capacitivecoupling of the capacitor C₁. At the time T₉, the precharge clock φ₁ isturned to a high level whereby the transistor Q₄ is turned on so thatthe clock φ_(6R) is turned to a high level. Thus, the control clockφ_(2R) is boosted to the original precharge level by capacitive couplingof the capacitor C₁.

According to the circuit of FIG. 11 as hereinabove described, thecut-off operation of the bit lines can be performed at a higher speedthan the circuit as shown in FIG. 3 while the clock φ₃ is prevented fromincluding any noise. Thus, the shared sense amplifier can be driven at ahigher speed by employing the circuit as shown in FIG. 11 in place ofthat shown in FIG. 3.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A driving circuit for a shared sense amplifierwhich drives at a high speed a shared sense amplifier circuit includingtwo pairs of bit lines respectively connected with memory cells, senseamplifier means provided between said two pairs of bit lines foramplifying information read from said memory cells, first switch meansinterposed between one of said pairs of bit lines and said senseamplifier means and second switch means interposed between the otherpair of bit lines and said sense amplifier means thereby to share saidsense amplifier means by said two pairs of bit lines, said drivingcircuit comprising:cut-off clock generation circuit means for generatinga cut-off clock responding at a high speed to addressing of said memorycells; decoder means for decoding said cut-off clock; and a controlclock generation circuit means for generating a first control clock forcontrolling the on-off operation of said first switch means and a secondcontrol clock for controlling the on-off operation of said second switchmeans, said cut-off clock generation circuit means including: a firstpotential level source, a second potential level source having apotential level different from that of said first potential levelsource, a first transistor having a first conducting terminal connectedto said first potential level source, a second transistor interposedbetween a second conducting terminal of said first transistor and saidsecond potential level source, first circuit means for making said firsttransistor conductive and said second transistor non-conductive inresponse to addressing of one of said memory cells, boosting capacitormeans interposed between said second conducting terminal of said firsttransistor and a gate terminal of said first transistor for making saidfirst transistor conductive at a high speed, and second circuit meansfor producing said cut-off clock on the basis of potential change atsaid second conducting terminal of said first transistor.
 2. A drivingcircuit for a shared sense amplifier in accordance with claim 1, whereinsaid first potential level source is a positive voltage source and saidsecond potential level source is a ground member.
 3. A driving circuitfor a shared sense amplifier in accordance with claim 2, wherein saidcontrol clock generation circuit means includes further capacitor meansfor precharging said first and second control clocks at a voltage levelexceeding that of said positive voltage source.
 4. A driving circuit fora shared sense amplifier in accordance with claim 3, wherein saidcontrol clock generation circuit means includes means for forciblydischarging the charge stored in said further capacitor means when saidcontrol clock falls.
 5. A driving circuit for a shared sense amplifierin accordance with claim 4 wherein said further capacitor meanscomprises two terminals, and further comprising a pair of dischargemeans for discharging said further capacitor means via both terminalsthereof.
 6. A driving circuit for a driving a shared sense amplifier athigh speed to read an addressed memory cell, the shared sense amplifiercircuit including two pairs of bit lines respectively connected withplural memory cells, sense amplifier means provided between said twopairs of bit lines for amplifying information read from said memorycells, first switch means interposed between one of said pairs of bitlines and said sense amplifier means and second switch means interposedbetween the other pair of bit lines and said sense amplifier meansthereby to share said sense amplifier means by said two pairs of bitlines, said driving circuit comprising:cut-off clock generation circuitmeans for generating a cut-off clock responding at a high speed toaddressing of said memory cells; decoder means for decoding said cut-offclock; and a control clock generation circuit means for generating afirst control clock for controlling the on-off operation of said firstswitch means and a second control clock for controlling the on-offoperation of said second switch means, said cut-off clock generationcircuit means including: a first potential level source, a secondpotential level source having a potential level different from that ofsaid first potential level source, a first transistor having a firstconducting terminal connected to said first potential level source, asecond transistor interposed between a second conducting terminal ofsaid first transistor and said second potential level source, firstcircuit means for making said first transistor conductive and saidsecond transistor non-conductive in response to addressing of one ofsaid memory cells, boosting capacitor means interposed between saidsecond conducting terminal of said first transistor and a gate terminalof said first transistor for making said first transistor conductive ata high speed, and second circuit means for producing said cut-off clockon the basis of potential change at said second conducting terminal ofsaid first transistor, said first circuit means including a thirdtransistor connected for driving the gate terminal of said firsttransistor, and a pair of transistors responsive to address signalsconnected to address the memory cells to be read, said pair oftransistors connected to operate said third transistor to drive the gateterminal of said first transistor in response to said address signals.7. A driving circuit for a driving a shared sense amplifier at highspeed to read an addressed memory cell as recited in claim 6 whereinsaid pair of transistors are parallel connected, having commonconnections at respective source and drain terminals thereof, andwherein each of said pair of transistors has a gate terminal, said gateterminals of said pair of transistors respectively driven bycomplementary address clock signals providing partial bits extractedfrom address data for the addressed memory cell.
 8. A driving circuitfor a driving a shared sense amplifier at high speed to read anaddressed memory cell as recited in claim 6 wherein said thirdtransistor includes first and second conducting terminals and a gateterminal, said first conducting terminal thereof connected to an addressstrobe signal, said second conducting terminal thereof connected to saidboost capacitor means, and said gate terminal thereof connected to acommon conducting terminal of said pair of transistors, andfurthercomprising a fourth transistor having a first conducting terminalconnected to said first potential level source, a second conductingterminal connected to said gate terminal of said third transistor, and agate terminal connected to a complemented form of said address strobesignal.
 9. A driving circuit for a driving a shared sense amplifier athigh speed to read an addressed memory cell as recited in claim 8further comprising a fifth transistor connected between said secondconducting terminal of said third transistor and said second potentiallevel source and having a gate terminal connected to a gate terminal ofsaid second transistor.
 10. A driving circuit for a driving a sharedsense amplifier at high speed to read an addressed memory cell asrecited in claim 8 wherein said pair of transistors are parallelconnected, having common connections at source and drain terminalsthereof, and wherein each of said pair of transistors has a gateterminal, said gate terminals of said pair of transistors respectivelydriven by complementary address clock signals providing partial bitsextracted from address data for the addressed memory cell.
 11. A drivingcircuit for a driving a shared sense amplifier at high speed to read anaddressed memory cell as recited in claim 10 wherein said second circuitmeans comprises a second pair of transistors, said second pair oftransistors being parallel connected to one another, and including afurther transistor having a gate terminal and first and secondconducting terminals, said first conducting terminal thereof connectedto said first potential level source, said second conducting terminalthereof connected to a common terminal of said second pair oftransistors, and said gate terminal thereof connected to said secondconducting terminal of said first transistor.
 12. A driving circuit fora driving a shared sense amplifier at high speed to read an addressedmemory cell as recited in claim 11 further comprising a fifth transistorconnected between said second conducting terminal of said thirdtransistor and said second potential level source and having a gateterminal connected to a gate terminal of said second transistor.
 13. Adriving circuit for a driving a shared sense amplifier at high speed toread an addressed memory cell as recited in claim 12 further including asixth transistor parallel connected with said second transistor to havecommonly connected respective first and second conducting terminals,saidsixth transistor having a gate terminal connected to said secondconducting terminal of said fourth transistor and to said gate terminalof said third transistor.
 14. A driving circuit for a driving a sharedsense amplifier at high speed to read an addressed memory cell asrecited in claim 13 wherein said second pair of transistors includes onetransistor having a gate terminal connected to said gate terminal ofsaid sixth transistor and another transistor having a gate terminalconnected to be driven by a complemented and delayed representation of adriving clock signal operable for activating and deactivating saidshared sense amplifier,said gate terminals of said second and fifthtransistors connected to be driven by said complemented and delayedrepresentation of said driving clock signal applied to said gateterminal of said another transistor of said second pair of transistors,an output clock signal of said cut-off clock generation circuit meansprovided at a junction of said second conducting terminal of saidfurther transistor and said common terminal of said second pair oftransistors.
 15. In a memory structure utilizing a shared senseamplifier circuit, the shared sense amplifier circuit including twopairs of bit lines respectively connected with plural memory cells,sense amplifier means provided between said two pairs of bit lines foramplifying information read from said memory cells, first switch meansinterposed between one of said pairs of bit lines and said senseamplifier means and second switch means interposed between the otherpair of bit lines and said sense amplifier means thereby to share saidsense amplifier means by said two pairs of bit lines, an improveddriving circuit comprising:cut-off clock generation circuit means forgenerating a cut-off clock responding at a high speed to addressing ofsaid memory cells; said cut-off clock generation circuit meansincluding: a first potential level source, a second potential levelsource having a potential level different from that of said firstpotential level source, a first transistor having a first conductingterminal connected to said first potential level source, a secondtransistor interposed between a second conducting terminal of said firsttransistor and said second potential level source, first circuit meansfor making said first transistor conductive and said second transistornon-conductive in response to addressing of one of said memory cells,boosting capacitor means interposed between said second conductingterminal of said first transistor and a gate terminal of said firsttransistor for making said first transistor conductive at a high speed,and second circuit means for producing said cut-off clock on the basisof potential change at said second conducting terminal of said firsttransistor, said first circuit means including a third transistorconnected for driving the gate terminal of said first transistor, and apair of transistors responsive to address signals connected to addressthe memory cells to be read, said pair of transistors connected tooperate said third transistor to drive the gate terminal of said firsttransistor in response to said address signals.
 16. An improved sharedsense amplifier memory structure as recited in claim 15, wherein:saidthird transistor includes first and second conducting terminals and agate terminal, said first conducting terminal thereof connected to anaddress strobe signal, said second conducting terminal thereof connectedto said boost capacitor means, and said gate terminal thereof connectedto a common conducting terminal of said pair of transistors, furthercomprising a fourth transistor having a first conducting terminalconnected to said first potential level source, a second conductingterminal connected to said gate terminal of said third transistor, and agate terminal connected to a complemented form of said address strobesignal, said pair of transistors being parallel connected, having commonconnections at source and drain terminals thereof, and each of said pairof transistors having a gate terminal, said gate terminals of said pairof transistors respectively driven by complementary address clocksignals providing partial bits extracted from address data for theaddressed memory cell, said second circuit means including a second pairof transistors, said second pair of transistors being parallel connectedto one another, and including a further transistor having a gateterminal and first and second conducting terminals, said firstconducting terminal thereof connected to said first potential levelsource, said second conducting terminal thereof connected to a commonterminal of said second pair of transistors, and said gate terminalthereof connected to said second conducting terminal of said firsttransistor, further including a fifth transistor connected between saidsecond conducting terminal of said third transistor and said secondpotential level source and having a gate terminal connected to a gateterminal of said second transistor, a sixth transistor parallelconnected with said second transistor to have commonly connectedrespective first and second conducting terminals, said sixth transistorhaving a gate terminal connected to said second conducting terminal ofsaid fourth transistor and to said gate terminal of said thirdtransistor, said second pair of transistors including one transistorhaving a gate terminal connected to said gate terminal of said sixthtransistor and another transistor having a gate terminal connected to bedriven by a complemented and delyaed representation of a driving clocksignal operable for activating and deactivating said shared senseamplifier, said gate terminals of said second and fifth transistorsconnected to be driven by said complemented and delayed representationof said driving clock signal applied to said gate terminal of saidanother transistor of said second pair of transistors, an output clocksignal of said cut-off clock generation circuit means provided at ajunction of said second conducting terminal of said further transistorand said common terminal of said second pair of transistors.